The invention relates generally to the field of input/output, or transceiver, circuits for use on integrated circuit chips to enable signals to be transmitted from, or received onto, an integrated circuit chip to and from external circuitry.
MOS circuits historically have had limited ability to sink current from, and source current into resistive loads, to drive very large capacitive loads at high speeds, and to afford high noise immunity. However, MOS circuits have improved in their switching speeds and recent short-channel MOS/VLSI technological advances have made even ECL-comparable performance possible in many applications.
As more and more functionality is integrated on-chip, the need for addressing the transient current behavior of MOS/VLSI chip interfaces becomes acute. In ECL designs, the peak current phenomena are dealt with by defining guidelines for packaging considerations (e.g. limiting pincount), but these specifications do not comprehend the high pincounts prevalent in MOS/VLSI designs today. The state-of-the-art in packaging is being sorely pressed by MOS circuit performance now.
The packaging affects the peak current characteristics of high performance MOS/VLSI parts because package pins have inductance. Voltage across an inductor is directly proportional to the inductance and to the rate of change of current through the inductor. Thus, as charge/discharge times decrease in larger capacitive loads, the time-compressed peak current transients can cause deleterious voltage rises at package pins, not to mention the phenomena created at the power/ground busses on-chip.
In new designs, several wires, each with a large capacitive load, are discharged through one ground pin. The need for current limiting is obvious in applications where worst-case speed specifications must be met at the slow corner of a process, even though the circuit may be as much as six times faster at the worst-case current corner of the same process.
In inherently noisy environments, such as a bus, the need for high noise immunity is great in order to guarantee data integrity. TTL technology has good noise characteristics, but MOS technology, with worst-case device threshold values less than 500 mV, is notoriously poor in applications where good low-state input voltage V.sub.il noise immunity is required.
A common way of compensating for deficiencies in MOS low-level noise immunity is by level-shifting, but a significant speed penalty may be exacted by the level-shifter stage.